give input at base and connect resistor at collector and 
gnd at emitter,vcc at collector finaaly take output at 
collector.

In series of Inverter is placed, the charge sharing happen 
between the input capacitance with the help of an load 
capacitane but we cant get the desired logical output. 

Remedies:

The load capacitane must be ten times greater than input 
capacitance.

Crosstalk is coupling effect of capacitance that takes place
between a weak net and an aggressor net

validation is a process where we test the chip on test board
they are basically test chips and are tested before coming
into routine production. 

Foundry people provide DRC rules

Synopsys

Foundry(Semiconductor Manufacturers)

LVs means LAyout versus schematic -method to check the
correctness of ur layout designed by cross checking with
netlist generated from schematic using the tool.
DRC means....??

DRC means Design Rules Checker - a tool for verifying the 
layout with the Physical layout design rules set so as to 
make sure that none of the rules have been violated.

LVS- LAYOUT VERSUS SHEMATIC TEST FROM NETLIST DESIGN
(NORMALLY MANUAL METHOD)
DRC-DESIGN RULE CHECK(EX SPICE TOOL WILL GENERATE ERRORS IF 
YOUR DESIGN NOT MET THE STANDARD DESIGN RULES)

LVS -LAYOUT VERSUS SHEMATIC TEST WHICH COMES IN THE 
STRACTURIAL DOMAIN IN WHICH WE WILL FIRST SHEMATIC THE 
CIRCUT AND AFTER BY USING TOOLS WE WILL MAKE THE LAYOUT BY 
COMAPARING THE BOTH THINGS JUST FOR SEEING WHEATHER ANY 
MISTAKES IS THERE OR NOT ...........IT IS TESTING PROCESS

DRC-DESIGN RULE CHECK THESE USEDE TESTING THE LAYOUT DESIGN 
AND FOR CHECKING THE CIRCUIT

Post layout extraction is neccessary to get the accurate 
netlist , with parasitic capacitance and rasistance. Post 
layout simulation are done using the extracted neltist  as 
this gives a better approximation of what the circuit 
behaviour would be in silicon.

g = gate, s= source, d= drain and b = bulk.

Cgs, Cgd, Cgb, Csd, Csb, Cdb. Out of this the largest is 
the Cgs becoz its value is linearly proportional to width 
of transistor and the Gate oxide which is the di-electric 
for this capacitance is the one which is engineered to have 
more dielectric constant and less thickness.

When a clock is triggered, if it reaches first to 
destination and next to source then we have a loss of  
data,or if it reaches first to source and later to 
destination we have a wrong result .this is called Clock 
skew,so it is necessary to a clock to reach simultaneously 
to source and destination.

clock skew is the time difference between the arrival of 
active clock edge to different flipflops of the same chip