Latch-up is a condition in which the parasitic components 
give rise to the Establishment of low resistance conducting 
path between VDD and VSS with Disastrous results. 

Latch up effect can be minimized by 1.putting the isolation 
between pmos and nmos regions. 
2. changing the dopping concentrations thus reducing the 
gain of pnpn device. 

SOI (silicon on insulator)doesnt have any latch up problem. 

because of latch up effect there is the short between power 
lines and the continuous current flows through the device 
till the power down. This results into malfunctioning of 
the device, resulting into its damage. This latch problem 
is observed in case of two transistors arranged side by 
side forming pnpn/npnp structure. (structure like SCR or 
thyristor).

Because we can't get full voltage swing with only NMOS or
PMOS ... we have to use both of them together for that purpose.

nmos passes a good 0 and a degraded 1 , whereas pmos passes 
a good 1 and bad 0. for pass transistor, both voltage 
levels need to be passed and hence both nmos and pkmmos 
need to be used.

delay increases

if we increase power supply to reduce delay ,delay will 
reduces but power dissipation will be high and to 
compensate the excessive power we have to increase die size 
which is impractical.

Delay increases

pd=f *c* vdd^2

power dissipation get increases.....
propagation delay get increases....
so speed of the circuit get decreased...