NOT

Not Same

CAN :- Implemented by boach
GMLAN:- Implemented for GM for vehicle network an diagnostics

in isr there is no return value but in function call there 
is return value

In function call the main program and the funtion have some 
relations but in ISR there is no need for this so there is 
no need of return value in ISR.

In case of a function call the arguments,local variables and
return address is stored in the stack where as in case of an
ISR, after executing the current instruction the context is
saved with no return value.

isr will be executed only when the system is interrupted 
whereas the function call meant for any operations to 
perform eventhough when there is no interrupt

Simply, an ISR (interrupt service routine) can be defined 
as a hardware function call. Generally, a CPU must 
immediately pay attention to a hardware interrupt call. An 
ISR is always given higher priority than a normal function 
call.

In a multiplexed bus system, many devices are connected to 
a common bus. If 2 or more devices attempt to use the bus 
at the same time , then data will be lost. Thus only one 
one device must be allowed to use the bus at a time. O e 
method is to connect the devices through tri-state 
devices , which when disabled will effectively discoonect 
devices from the bus.

yes we can create..

No,we can't

No we cannot create a table without primary key

It's a combination of software and hardware Which are 
embedded by Kiel compiler.It 1s a device that do a specific 
task.

it is a combination of hardware and software to perform 
desired task

where the software is embedding into the hardware is called 
embedded. here software is embedded into haraware by using 
device programmer.

Embedded System is nothing but a combination of Hardware
with dedicated software designed for the specific application

Embedded System is one which performs one didicated task 
with dedicated hardware and software and over which user 
can not add and remove h/w and s/w. May be system hard or 
soft real time.

Embedded system means that the software provied the
intellengence to the electronic

embedded system is a combination of h/w n s/w for the 
execution of a desired task repeatedly...

pruthvi is right only to a certain extent.

In short, Embedded System gives intelligence to machines. 
Machines may be either electrical or electronic or 
mechanical or a combination of all.

xor ax, ax
loop1:
        call foo
        inc al
        cmp ax, 10
        jb loop1

mov ro,#10h

here:
        acall fun
        inc   a1
        djnz  ro,here

org 00h
mov r0,#09
mov r1,#01
loop : acall func;    ; calling function in loop 9-0 times
       djnz r0,loop


func : inc r1 ; output will be in r1 register
       ret

end


if any thing plz mail to me laxman_balu@hotmail.com

Add the digits and check the sum. It would imply a 3-bit 
adder (max. value = 8 can be represented with three bits) 
and compare the result to 011.

3 input AND those 3 bits. No adder needed...

for serially arriving stream: 
use a 2 bit accumulator( S1 and S2) with outputs O1 and O2. 
Final Output will be Y = ~O1 . O2

For parallel, 
use combinational logic , probably priority encoder to
reduce  delay.

keep the number in A reg and ratate it 8 times if carry 
generates more than 3  it will indicate a non desired numer

step1: start
step2: mov the byte to accumulator
step3: intialize length = 0 , count = 0
step4: rotate acc. to right through carry.
step5: if carry = 1 , increment count
step6: increment length
step7: if length < 8 , goto step3
step8: if count = 3 , (do required action)
step9: end

Step 1:  Store the 8 bit value in a accumulator

Step 2:  Store 0x1 in a register0, initialize two counter  
with 0 i.e. store zero in a reg1 and reg2.

LOOP:
Step 3:  Check if AND operation between the value in
register0 and accumulator is set i.e. 1 
if yes, increment reg1 and reg2
If no, increment only reg2

step 4: Left shift the value of register0 by 1
step 5: if ( reg2 >=8), exit LOOP
                 if ( reg1 >= 3), show that 3 bit is set
        Else Go To LOOP



MOV XAR1, #Data
MOV XAR0, #0
MOV XAR2, #0

Loop:
TBIT *XAR1, #Count 
BF Loop1, NTC
INR *XAR0

Loop1:
INR *XAR2
MOV AL, *XAR1
CMP AL, #0x03
BF Loop3, EQ

MOV AL, *XAR2
CMP AL, #0x80
BF Loop, NEQ

Loop3:
EXIT

Sorry thr was a bit mistake. Corrected : 

MOV XAR1, #Data
MOV XAR0, #0
MOV XAR2, #0

Loop:
TBIT *XAR1, *XAR2 
BF Loop1, NTC
INR *XAR0

Loop1:
INR *XAR2
MOV AL, *XAR0
CMP AL, #0x03
BF Loop3, EQ

MOV AL, *XAR2
CMP AL, #0x80
BF Loop, NEQ

Loop3:
EXIT

I have modified it a bit,

MOVL XAR1, #Data
MOVL XAR0, #0x00
MOVL XAR2, #0x00

Loop:
TBIT *XAR1,#XAR2 
BF Loop1, NTC
INR AR0

Loop1:
INR AR2
MOV AL, *XAR0
CMP AL, @0x03
BF Action, EQ

MOV AL, *XAR2
CMP AL, @0x08
BF Loop, NEQ

Loop3:
EXIT

Action:

You fools...the question is to design a circuit
(hardware)..not writing a program.

make a 4-bit adder/subtractor ( which can perform A+B and A-
B depending on value of bit say SUB..ie if SUB is 1 it will 
perform A+B ) now give A and B as inputs and make MSB of B 
as SUB bit.
suppose A=0110(6),B=1110(-2);so result will be A-B ie.,   
A+|B|=6-(-2)=8

binary counter with the number of bits available. 
initiallly counter is set to zero. then bits are checked 
against logic 1 or 0,if they are either logic 1 or 0,then 
counter is incremented.

in binary counter the flip flop of lowest order position is 
complemented with every pulse.this means that JK input 
position must me maintained with logic one

Charging a Capacitor:

The voltage across the capacitor is not instantaneously 
equal to that of the voltage across the battery when the 
switch is closed. The voltage on the capacitor builds up as 
more and more charges flows onto the capacitor until the 
battery is no longer able to "push" any more charge onto 
the capacitor, at which point the capacitor becomes fully 
charged.
The initial flow of charges from the battery to the 
capacitor means that there is a current flowing through the 
system until the capacitor is charged. This current flow 
decays exponentially from some initial value to zero.
DisCharging a Capacitor:
Switch remains open and voltage across capaciotr decreses 
untill it reaches zero.

the capacitor is charge when the current flow through the
ckt and its discharge whenever appllied voltage is stopped.

Capacitor is made of say two plates seperated by dielctic 
material. When volage is apllied the ions on the plate are 
zero so initially more current will flow like in short 
circuit.
As time passes the charges(+ve and -ve) accumalate on 
plates over a time and it opposes current flow. Now we say 
capacitor charged fully. Now the time taken to charge fully 
is called time constant of a capacitor. This time can be 
varied by connecting a resistor in series with capacitor. 
When high resisor is connected voltage drop across 
capacitor is reduced so it take long time to charge fully.
Vica-versa for low resitor. The relation is exponetial 
charging and discharging. Discharging process is also 
similar way.

-----By RAHUL SINGHAL----
----This is the code of a FSM that implements a toll booth -
----controller


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ----using all functions of 
specific package---

ENTITY tollbooth2 IS
   PORT (Clock,car_s,RE : IN STD_LOGIC;
         coin_s         : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
         r_light,g_light,alarm : OUT STD_LOGIC);
END tollbooth2;

ARCHITECTURE Behav OF tollbooth2 IS
TYPE state_type IS 
(NO_CAR,GOTZERO,GOTFIV,GOTTEN,GOTFIF,GOTTWEN,CAR_PAID,CHEATE
D);
------GOTZERO = PAID $0.00--------- 
------GOTFIV = PAID $0.05----------
------GOTTEN = PAID $0.10----------
------GOTFIF = PAID $0.15----------
------GOTTWEN = PAID $0.20---------
SIGNAL present_state,next_state : state_type;

BEGIN
-----Next state is identified using present state,car & 
coin sensors------
    PROCESS(present_state,car_s,coin_s)
     BEGIN
     
     CASE present_state IS
      WHEN NO_CAR =>
       IF (car_s = '1') THEN
           next_state <= GOTZERO;
        ELSE 
           next_state <= NO_CAR;
       END IF;

     WHEN GOTZERO =>
      IF (car_s ='0') THEN
      next_state <= CHEATED;
        ELSIF (coin_s = "00") THEN
        next_state <= GOTZERO;
        ELSIF (coin_s = "01") THEN
         next_state <= GOTFIV;
        ELSIF (coin_s ="10") THEN
         next_state <= GOTTEN;
      END IF;

    WHEN GOTFIV=>
     IF (car_s ='0') THEN
      next_state <= CHEATED;
       ELSIF (coin_s = "00") THEN
       next_state <= GOTFIV;
  
       ELSIF (coin_s = "01") THEN
        next_state <= GOTTEN;
       ELSIF (coin_s <= "10") THEN
        next_state <= GOTFIV;
    END IF;

   WHEN GOTTEN =>
    IF (car_s ='0') THEN
      next_state <= CHEATED;
      ELSIF (coin_s ="00") THEN
      next_state <= GOTTEN;
      
      ELSIF (coin_s="01") THEN
         next_state <= GOTFIV;
      ELSIF (coin_s="10") THEN
         next_state <= GOTTWEN;
    END IF;

   WHEN GOTFIF =>
    IF (car_s ='0') THEN
       next_state <= CHEATED; 
       ELSIF (coin_s = "00") THEN
       next_state <= GOTFIF;
      
       ELSIF (coin_s ="01") THEN
           next_state <= GOTTWEN;
       ELSIF (coin_s = "10") THEN
           next_state <= GOTTWEN;
     END IF;

   WHEN GOTTWEN =>
      next_state <= CAR_PAID;

   WHEN CAR_PAID =>
    IF (car_s = '0') THEN
      next_state <= NO_CAR;
     ELSE
      next_state<= CAR_PAID;
   END IF;
 
  WHEN CHEATED =>
      IF (car_s = '1') THEN
      next_state <= GOTZERO;
      ELSE 
      next_state <= CHEATED;
  END IF;

END CASE;
END PROCESS;-----End of Process 1
-------PROCESS 2 for STATE REGISTER CLOCKING--------
PROCESS(Clock,RE)
  BEGIN
   IF RE = '1' THEN
      present_state <= GOTZERO;
----When the clock changes from low to high,the state of 
the system
----stored in next_state becomes the present state----- 
       ELSIF Clock'EVENT AND Clock ='1' THEN
      present_state <= next_state;
   END IF; 
  END PROCESS;-----End of Process 2-------
---------------------------------------------------------
-----Conditional signal assignment statements----------
r_light <= '0' WHEN present_state = CAR_PAID ELSE '1';
g_light <= '1' WHEN present_state = CAR_PAID ELSE '0';
alarm <= '1' WHEN present_state = CHEATED ELSE '0';
END Behav;

try finite state machine logic it will definitely give the 
output

By using XNOR gate if the signals are same then only the 
output will be one otherwise not.

by using X-OR(Exclusive-OR ) gate and checking using zero 
flag ( it should be set if two 8-bit signals are same) . 
also the accumulator contents will also become all bits 
areoooo oooo.

PVSReddy is correct answer.

In Ex-OR gate:
1 - 1:0
1 - 0:1
0 - 1:1
0 - 0:0

put one bubble in front of xor gate....