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how 2 design a mod 6 synchronous counter using jk flip flop?
 Question Submitted By :: Electronics-Communications
I also faced this Question!!     Answer Posted By  
# 1
binary for 6 is 110..we will need 3 MS JK FF i.e. using ic
7476....we need to design a truth table for that...
till state 0 to 5(6 states) put your o/p as those
are valid states and for the remaining ones those are the
invalid states....then draw k-map and design the
combinational logic....put all ur preset and J0 K0..i/ps of
FF to logic 1 and accordingly clock the FF
and put the o/p of the combinaional logic to the clear of
thr order to clear the states after 5th.....

hope this was usefull....
Is This Answer Correct ?    31 Yes 7 No
# 2
mod-6 counter has 6 states,i.e, 0 to 5.
the binary form of 6 is 110, therefore 3 jk flipflops are
required to represent each bit. the ic used is 7476 or 74112.
first one should be clear with exitation table of jk.
then we should construct the transition table consisting of
present states, next states and flip flop inputs.. then
using this table k-map should be filled to obtain the design
equations for the circiut.lastly circiut should be
implemented and should be checked for proper working.
Is This Answer Correct ?    4 Yes 2 No
# 3
mod-3 synchronous counter using j-k flipflop 
Is This Answer Correct ?    24 Yes 31 No
Jignesh Patel

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