| Other VLSI Interview Questions |
| |
| Question | Asked @ | Answers |
| |
| Explain the various Capacitances associated with a
transistor and which one of them is the most prominent? | Intel | 1 |
| Which gate is normally preferred while implementing circuits
using CMOS logic, NAND or NOR? Why? | Intel | 6 |
| Explain the difference between write through and write back
cache. | Intel | 1 |
| What is Noise Margin? Explain the procedure to determine
Noise Margin? | Cisco | 2 |
| Explain Clock Skew? | Intel | 2 |
| what is Latch up?How to avoid Latch up? | | 2 |
| For a 0.18um and 0.8um technology MOSFET, which has a higher
cutoff frequency? | | 1 |
| What is SPICE? | Intel | 1 |
| What are set up time & hold time constraints? What do they
signify? | | 1 |
| Give the various techniques you know to minimize power
consumption? | | 3 |
| How do you detect a sequence of "1101" arriving serially
from a signal line?
| nvidia | 2 |
| Factors affecting Power Consumption on a chip? | Intel | 1 |
| Differences between DRAM and SRAM? | Intel | 4 |
| What is validation? | Intel | 1 |
| what is Early effects and their physical origin. | | 1 |
| Differences between Signals and Variables in VHDL? If the
same code is written using Signals and Variables what does
it synthesize to? | Intel | 1 |
| What is LVS, DRC? | Intel | 4 |
| How does Resistance of the metal lines vary with increasing
thickness and increasing length? | | 1 |
| Have you studied pipelining? List the 5 stages of a 5 stage
pipeline. Assuming 1 clock per stage, what is the latency
of an instruction in a 5 stage machine? What is the
throughput of this machine ? | Intel | 2 |
| What is a linked list? Explain the 2 fields in a linked list? | Intel | 1 |
| |
| For more VLSI Interview Questions Click Here |
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