ALLInterview.com :: Home Page            
 Advertise your Business Here     
Browse  |   Placement Papers  |   Company  |   Code Snippets  |   Certifications  |   Visa Questions
Post Question  |   Post Answer  |   My Panel  |   Search  |   Articles  |   Topics  |   ERRORS new
   Refer this Site  Refer This Site to Your Friends  Site Map  Bookmark this Site  Set it as your HomePage  Contact Us     Login  |  Sign Up                      
Google
   
 
Categories >> Engineering >> Electronics Communications
 
 


 

 
 Civil Engineering interview questions  Civil Engineering Interview Questions (3147)
 Mechanical Engineering interview questions  Mechanical Engineering Interview Questions (3304)
 Electrical Engineering interview questions  Electrical Engineering Interview Questions (13469)
 Electronics Communications interview questions  Electronics Communications Interview Questions (2392)
 Chemical Engineering interview questions  Chemical Engineering Interview Questions (423)
 Aeronautical Engineering interview questions  Aeronautical Engineering Interview Questions (77)
 Bio Engineering interview questions  Bio Engineering Interview Questions (17)
 Metallurgy interview questions  Metallurgy Interview Questions (80)
 Industrial Engineering interview questions  Industrial Engineering Interview Questions (166)
 Instrumentation interview questions  Instrumentation Interview Questions (2407)
 Automobile Engineering interview questions  Automobile Engineering Interview Questions (107)
 Mechatronics Engineering interview questions  Mechatronics Engineering Interview Questions (38)
 Marine Engineering interview questions  Marine Engineering Interview Questions (45)
 Power Plant Engineering interview questions  Power Plant Engineering Interview Questions (81)
 Engineering AllOther interview questions  Engineering AllOther Interview Questions (1204)
Question
what is race around condition
 Question Submitted By :: Electronics-Communications
I also faced this Question!!     Answer Posted By  
 
Answer
# 1
we know that when j=k=1 in a jk flip flop then output is
the complement of the previous output i.e if j=k=1 and Y=0
then after the clock pulse y becomes 1.
but if the propagation delay of the gates is much lesser
than the pulse duration then during the same pulse at first
y becomes 0 and after another propagation delay y becomes 1
and so on.
thus within the same pulse duration due to very small
propagation delays output oscillates back and forth between
0 and 1. this condition is called race around condition and
at the end of the pulse the output is uncertain.
 
Is This Answer Correct ?    237 Yes 6 No
Baisakhi Khasnabis
 
Answer
# 2
when we put j=1 and k=1 in j-k flip flop, the output, Q
toggles to 0 and 1 continuously; and it becomes uncertain
to predict the output. This condition is known as Race
around condition.
It can be rectified using Master-Slave flip flop.
 
Is This Answer Correct ?    164 Yes 29 No
Anshuman Kumar Chanchal
 
 
 
Answer
# 3
in simple jk flip flor circuit
at condition
j=1 and k=1
every time output toggle w.r.t previous output,we use
single clock in this case so that condition known as race
around condition.by using master slave jk flip flop we can
remove this problem.
 
Is This Answer Correct ?    165 Yes 42 No
Sahil Gupta
 
Answer
# 4
A fliplflop is a basic digital memory circuit.In JK
flipflop when the clock pulse is equal to 1 and also when
j=k=1 , we know that the next state is complement of the
present state.but at that instance if clock pulse is
still '1'(high)the o/p again complements.and it repeats
untill clk puls goes back to '0'.this is race aroud conditn.

This is because that clk puls duratn is more than the
propagatn delay of flipflop.to avoid this we need to adjust
the clk pulse duratn or we need to put restriction on clk
pulse width as
clk pls (t)<propgatn delay using mater slave configuratn
 
Is This Answer Correct ?    51 Yes 12 No
Sowmya
 
Answer
# 5
we know that when j=k=1 in a jk flip flop then output is
the complement of the previous output i.e if j=k=1 and Y=0
then after the clock pulse y becomes 1.
but if the propagation delay of the gates is much lesser
than the pulse duration then during the same pulse at first
y becomes 0 and after another propagation delay y becomes 1
and so on.
thus within the same pulse duration due to very small
propagation delays output oscillates back and forth between
0 and 1. this condition is called race around condition and
at the end of the pulse the output is uncertain.
so this can be avoided by using only edgetriggerd ff
rahter than using level triggerd.
 
Is This Answer Correct ?    20 Yes 4 No
Abhinandan Kumar
 
Answer
# 6
In a JK flip flop when J=1 and K=1 and clock is applied, the
outputs keep on toggling at every delay time of the flip
flop as long as the clock is present.Hence the output at the
end of the clock pulse is ambiguous.This condition is called
race around condition.
 
Is This Answer Correct ?    16 Yes 8 No
Nidhi , B.tech 2nd Year ,r.v.s
 
Answer
# 7
it is timing problem,caused because in the time of tiggering
clock pulse stays in a high state for along time as compare
to propagation delay.
 
Is This Answer Correct ?    16 Yes 11 No
Ravi Pandey B.tech. A.i.t.s.h
 
Answer
# 8
simple jk flip flor circuit
at condition
j=1 and k=1
thus within the same pulse duration due to very small
propagation delays output oscillates back and forth between
0 and 1. this condition is called race around condition and
at the end of the pulse the output is uncertain.
 
Is This Answer Correct ?    5 Yes 0 No
Neeraj Kumar
 
Answer
# 9
when we put j=1 and k=1 in j-k flip flop, the output, Q
toggles to 0 and 1 continuously; and it becomes uncertain
to predict the output. This condition is known as Race
around condition.
It can be rectified using Master-Slave flip flop.
 
Is This Answer Correct ?    4 Yes 0 No
Ajay Yadav
 
Answer
# 10
we know that when j=k=1 in a jk flip flop then output is
the complement of the previous output i.e if j=k=1 and Y=0
then after the clock pulse y becomes 1.
but if the propagation delay of the gates is much lesser
than the pulse duration then during the same pulse at first
y becomes 0 and after another propagation delay y becomes 1
and so on.
thus within the same pulse duration due to very small
propagation delays output oscillates back and forth between
0 and 1. this condition is called race around condition and
at the end of the pulse the output is uncertain.
 
Is This Answer Correct ?    6 Yes 4 No
Ekta
 

 
 
 
Other Electronics Communications Interview Questions
 
  Question Asked @ Answers
 
what is the mean of electronics in hindi ? TCS 6
In the 8421 BCD code the decimal number 125 is written as???   4
Mention the operators that cannot be overloaded?   1
WHAT IS TRANSISTER HCL 7
What is main difference in PDH and SDH Tech.   3
Usually we say that capacitors block dc and allow ac. if a capacitior is connect in series with a resistance.. will current pass through the capacitior.... if i doesn't pass..is it due to offering of infinite resistance by capacitor there by acting as a open....   1
what is the different between opamp,comparator and amplifier?   2
What is DRX? Why do we need it?   1
Give condition for conduction of UJT? TATA 1
what is embedded system TCS 3
When an inductor tunes at 200 KHz with 624 pF capacitor and at 600 KHz with 60.4 pF capacitor then the self capacitance of the inductor would be a) 8.05 pF b) 10.05pF c.) 16.01pF d.) 20.01pF BSNL 3
what is difference between voltage & current?   4
 
For more Electronics Communications Interview Questions Click Here 
 
 
 
 
 


   
Copyright Policy  |  Terms of Service  |  Articles  |  Site Map  |  RSS Site Map  |  Contact Us
   
Copyright 2013  ALLInterview.com.  All Rights Reserved.

ALLInterview.com   ::  KalAajKal.com