Requirements        -         UAT
\                             /
Specifications      -     System testing
  \                          /
Detailed design     -     Integration Testing
   \                        /
Implementation code -     unit test


the V-concept of the testing process 1s shown here.

V-Model is a graphical representation of SDLC.

The left tail of the V represents the specification stream 
where the system specifications are defined. The right tail 
of the V represents the testing stream where the systems 
are being tested (against the specifications defined on the 
left-tail). The bottom of the V where the tails meet, 
represents the development stream.