| Other VLSI Interview Questions |
| |
| Question | Asked @ | Answers |
| |
| What are the different limitations in increasing the power
supply to reduce delay? | | 1 |
| What is charge sharing? | Intel | 1 |
| What is SPICE? | Intel | 1 |
| What are set up time & hold time constraints? What do they
signify? | | 1 |
| Why is Extraction performed? | Intel | 1 |
| Are you familiar with VHDL and/or Verilog? | Intel | 4 |
| For a single computer processor computer system, what is the
purpose of a processor cache and describe its operation? | Intel | 1 |
| Implement F = AB+C using CMOS gates? | Intel | 1 |
| what is short Channel effect. | | 1 |
| Are you familiar with the term MESI? | Intel | 1 |
| Differences between DRAM and SRAM? | Intel | 4 |
| Which gate is normally preferred while implementing circuits
using CMOS logic, NAND or NOR? Why? | Intel | 6 |
| what is Latch up?How to avoid Latch up? | | 2 |
| What is interrupt latency? | | 2 |
| What products have you designed which have entered high
volume production? | Intel | 1 |
| Give the various techniques you know to minimize power
consumption? | | 3 |
| What is validation? | Intel | 1 |
| What is Cross Talk? | Intel | 2 |
| What happens to delay if we include a resistance at the
output of a CMOS circuit? | | 1 |
| Differences between Signals and Variables in VHDL? If the
same code is written using Signals and Variables what does
it synthesize to? | Intel | 1 |
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