| Other VLSI Interview Questions |
| |
| Question | Asked @ | Answers |
| |
| Differences between blocking and Non-blocking statements in
Verilog? | Intel | 3 |
| For a 0.18um and 0.8um technology MOSFET, which has a higher
cutoff frequency? | | 1 |
| Implement F = AB+C using CMOS gates? | Intel | 1 |
| what is body effect? | | 1 |
| Define threshold voltage? | Intel | 3 |
| Why is Extraction performed? | Intel | 1 |
| What are the limitations in increasing the power supply to
reduce delay? | | 1 |
| Implement an Inverter using a single transistor? | Intel | 1 |
| What are the two types of noise of MOSFET, how to eliminate
them?(Thermal and Flicker). | Analog-Devices | 2 |
| Suppose you have a combinational circuit between two
registers driven by a clock. What will you do if the delay
of the combinational circuit is greater than your clock
signal? (You can't resize the combinational circuit
transistors)
| | 3 |
| Are you familiar with VHDL and/or Verilog? | Intel | 4 |
| Explain the concept of a Clock Divider Circuit? Write a VHDL
code for the same? | Intel | 1 |
| What is charge sharing? | Intel | 1 |
| Explain Clock Skew? | Intel | 2 |
| What is interrupt latency? | | 2 |
| Who provides the DRC rules? | Intel | 3 |
| What is validation? | Intel | 1 |
| For a single computer processor computer system, what is the
purpose of a processor cache and describe its operation? | Intel | 1 |
| Have you studied pipelining? List the 5 stages of a 5 stage
pipeline. Assuming 1 clock per stage, what is the latency
of an instruction in a 5 stage machine? What is the
throughput of this machine ? | Intel | 2 |
| What types of high speed CMOS circuits have you designed? | Intel | 1 |
| |
| For more VLSI Interview Questions Click Here |
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