| Other VLSI Interview Questions |
| |
| Question | Asked @ | Answers |
| |
| Suppose you have a combinational circuit between two
registers driven by a clock. What will you do if the delay
of the combinational circuit is greater than your clock
signal? (You can't resize the combinational circuit
transistors)
| | 3 |
| A circuit has 1 input X and 2 outputs A and B. If X = HIGH
for 4 clock ticks, A = 1. If X = LOW for 4 clock ticks, B =
1. Draw a state diagram for this Spec? | Intel | 1 |
| What is validation? | Intel | 1 |
| How many bit combinations are there in a byte? | Intel | 4 |
| Give the various techniques you know to minimize power
consumption? | | 3 |
| What are the different limitations in increasing the power
supply to reduce delay? | | 1 |
| Explain the concept of a Clock Divider Circuit? Write a VHDL
code for the same? | Intel | 1 |
| Have you studied pipelining? List the 5 stages of a 5 stage
pipeline. Assuming 1 clock per stage, what is the latency of
an instruction in a 5 stage machine? What is the throughput
of this machine ? | Intel | 2 |
| Differences between blocking and Non-blocking statements in
Verilog? | Intel | 3 |
| What are the two types of noise of MOSFET, how to eliminate
them?(Thermal and Flicker). | Analog-Devices | 2 |
| What happens to delay if you increase load capacitance? | | 2 |
| Are you familiar with the term snooping? | Intel | 1 |
| What is Cross Talk? | Intel | 2 |
| What is FPGA? | Intel | 2 |
| How to find the read failiure probablity in SRAM?
| | 1 |
| Are you familiar with VHDL and/or Verilog? | Intel | 4 |
| Why don?t we use just one NMOS or PMOS transistor as a
transmission gate? | | 2 |
| What products have you designed which have entered high
volume production? | Intel | 1 |
| Implement D flip-flop with a couple of latches? Write a VHDL
Code for a D flip-flop? | Intel | 3 |
| What happens when the gate oxide is very thin? | Intel | 2 |
| |
| For more VLSI Interview Questions Click Here |
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