NAND gate is normally prefered because the mobility of 
holes in NAND gate is three times greater than mobility of 
electron.

if u look at the structure of cmos-nand gate,u cud find the
parallel pmos pull-up transistor configuration whereas in
cmos-nor gate its series config,so the effective resistance
offered by 2-pmos transistors even when they r conducting
due to small Rds (drain-to-source resistance)are smaller in
comparison to the same offered by series pmos in nor
gate..hence the current delivered to the output during HIGH
o/p condition is more for nand gate,due to which it has the
ability to drive more no. of loads of similar type ,thus
offer improved FAN-OUT than cmos-nor gate. 
I feel tat this could be the reason..it is true fact as per
WAKERLY text book..but there cud be 'n' no of other reasons
too..think over 

thankx..
balaji kalluri

NAAND gate is more preferred than NOR because high to low
and low to high transition time is less in NAND as compared
to NOR

As because the logical effort of Nand gate is lower than
that of the Nor gate the time taken to drive same capacitor
with same input slew is lesser for Nand that that of Nor.
Means Nand is faster than Nor.

nand gate is preferred because it has high driving 
capacity.

NAND is a better gate for design than NOR because at the 
transistor level the mobility of electrons of NAND is 
normally three times that of holes compared to NOR and thus 
the NAND is a faster gate. The gate-leakage in NAND 
structures is much lower. If you consider t_phl and t_plh 
delays you will find that it is more symmetric in case of 
NAND (the delay profile), but for NOR, one delay is much 
higher than the other(obviously t_plh is higher since the 
higher resistance PMOSs are in series connection which 
again increases the resistance).