IN SPARTAN 3E BOARD.. THE INTERNAL CLOCK FREQUENCY IS 
16MHZ... IF WE WANT TO INTERFACING THE EXT DIPLAY DEVICES
WE WON'T RUN IT WITH A NORMAL CLOCK FREQ(16 
MHZ)....THATSWHY I HAVE TO CREATED NEW CLOCK PULSE WITH THE 
FREQ OF 1HZ BY DEVIDING THE CLOCK..... TAKE THE NORMAL CLK 
AS A REFERENCE...THIS IS KNOWN AS CLOCK DIVIDER CONCEPT...

ENTITY CLK_DIV IS
    PORT(CLK: IN STD_LOGIC;
          NEWCLK:OUT STD_LOGIC);
END CLK_DIV
ARCH BEH OF CLK_DIV IS
VARIABLE COUNT:INTEGER:=0;
SIGNAL CLKN:STD_LOGIC; 
BEGIN
PROCESS(CLK)
BEGIN
IF CLK='1' AND CLK'EVENT THEN
COUNT:=COUNT+1;
IF COUNT=8000000 THEN
    NEWCLK<= NOT CLKN 
    COUNT:=0;
END PROCESS;
END BEH;