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 86 Family Interview Questions VLSI Interview Questions DSP Interview Questions Embedded Systems AllOther Interview Questions
Question
```Explain the concept of a Clock Divider Circuit? Write a VHDL
code for the same?```
Question Submitted By :: Markus
I also faced this Question!!     Rank Answer Posted By

Re: Explain the concept of a Clock Divider Circuit? Write a VHDL code for the same?
# 1

IN SPARTAN 3E BOARD.. THE INTERNAL CLOCK FREQUENCY IS
16MHZ... IF WE WANT TO INTERFACING THE EXT DIPLAY DEVICES
WE WON'T RUN IT WITH A NORMAL CLOCK FREQ(16
MHZ)....THATSWHY I HAVE TO CREATED NEW CLOCK PULSE WITH THE
FREQ OF 1HZ BY DEVIDING THE CLOCK..... TAKE THE NORMAL CLK
AS A REFERENCE...THIS IS KNOWN AS CLOCK DIVIDER CONCEPT...

ENTITY CLK_DIV IS
PORT(CLK: IN STD_LOGIC;
NEWCLK:OUT STD_LOGIC);
END CLK_DIV
ARCH BEH OF CLK_DIV IS
VARIABLE COUNT:INTEGER:=0;
SIGNAL CLKN:STD_LOGIC;
BEGIN
PROCESS(CLK)
BEGIN
IF CLK='1' AND CLK'EVENT THEN
COUNT:=COUNT+1;
IF COUNT=8000000 THEN
NEWCLK<= NOT CLKN
COUNT:=0;
END PROCESS;
END BEH;

 Is This Answer Correct ? 19 Yes 12 No
Jaya Suriya

Re: Explain the concept of a Clock Divider Circuit? Write a VHDL code for the same?
# 2
I am using the Mr.Suriya code with little modification.

ENTITY CLK_DIV IS
PORT(CLK: IN STD_LOGIC;
NEWCLK:OUT STD_LOGIC);
END CLK_DIV
ARCH BEH OF CLK_DIV IS
VARIABLE COUNT:INTEGER:=0;
BEGIN
PROCESS(CLK)
BEGIN
IF CLK='1' AND CLK'EVENT THEN
COUNT:=COUNT+1;
IF COUNT=8000000 THEN
NEWCLK<= '1';
COUNT:=0;
ELSE
NEWCLK<= '0';
END IF;
END IF;
END PROCESS;
END BEH;

 Is This Answer Correct ? 12 Yes 11 No
Senthil

Re: Explain the concept of a Clock Divider Circuit? Write a VHDL code for the same?
# 3
please initialize the variables before using it in the
behaviour architecture or else it will be in the unknown
state still it has some legal value.

 Is This Answer Correct ? 2 Yes 3 No
Manju

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