| Other VLSI Interview Questions |
| |
| Question | Asked @ | Answers |
| |
| Which gate is normally preferred while implementing circuits
using CMOS logic, NAND or NOR? Why? | Intel | 6 |
| Are you familiar with the term snooping? | Intel | 1 |
| What is setup time and hold time? | Intel | 1 |
| What is SPICE? | Intel | 1 |
| A circuit has 1 input X and 2 outputs A and B. If X = HIGH
for 4 clock ticks, A = 1. If X = LOW for 4 clock ticks, B =
1. Draw a state diagram for this Spec? | Intel | 1 |
| Give the expression for CMOS switching power dissipation? | | 2 |
| For f = AB+CD if B is S-a-1, what r the test vectors needed
to detect the fault? | Intel | 1 |
| what is body effect? | | 1 |
| Differences between DRAM and SRAM? | Intel | 4 |
| Have you studied buses? What types? | Intel | 1 |
| In what cases do you need to double clock a signal before
presenting it to a synchronous state machine? | Intel | 2 |
| Differences between D-Latch and D flip-flop? | Intel | 6 |
| Define threshold voltage? | Intel | 3 |
| What happens to delay if we include a resistance at the
output of a CMOS circuit? | | 1 |
| What is LVS, DRC? | Intel | 4 |
| What is interrupt latency? | | 2 |
| What are the main issues associated with multiprocessor
caches and how might you solve them? | Intel | 1 |
| Who provides the DRC rules? | Intel | 3 |
| Explain Clock Skew? | Intel | 2 |
| what is short Channel effect. | | 1 |
| |
| For more VLSI Interview Questions Click Here |
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