| Other VLSI Interview Questions |
| |
| Question | Asked @ | Answers |
| |
| Are you familiar with VHDL and/or Verilog? | Intel | 4 |
| Differences between Signals and Variables in VHDL? If the
same code is written using Signals and Variables what does
it synthesize to? | Intel | 1 |
| Give the expression for CMOS switching power dissipation? | | 2 |
| Differences between blocking and Non-blocking statements in
Verilog? | Intel | 3 |
| Why don?t we use just one NMOS or PMOS transistor as a
transmission gate? | | 2 |
| What is interrupt latency? | | 2 |
| In what cases do you need to double clock a signal before
presenting it to a synchronous state machine? | Intel | 2 |
| Explain about stuck at fault models, scan design, BIST and
IDDQ testing? | Intel | 1 |
| What is validation? | Intel | 1 |
| What is Cross Talk? | Intel | 2 |
| Have you studied pipelining? List the 5 stages of a 5 stage
pipeline. Assuming 1 clock per stage, what is the latency
of an instruction in a 5 stage machine? What is the
throughput of this machine ? | Intel | 2 |
| Explain the concept of a Clock Divider Circuit? Write a VHDL
code for the same? | Intel | 1 |
| How to find the read failiure probablity in SRAM?
| | 1 |
| What are the different limitations in increasing the power
supply to reduce delay? | | 1 |
| what is Latch up?How to avoid Latch up? | | 2 |
| what is Early effects and their physical origin. | | 1 |
| For a 0.18um and 0.8um technology MOSFET, which has a higher
cutoff frequency? | | 1 |
| Implement D flip-flop with a couple of latches? Write a VHDL
Code for a D flip-flop? | Intel | 3 |
| What is SPICE? | Intel | 1 |
| How does Resistance of the metal lines vary with increasing
thickness and increasing length? | | 1 |
| |
| For more VLSI Interview Questions Click Here |
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