| Other VLSI Interview Questions |
| |
| Question | Asked @ | Answers |
| |
| what is short Channel effect. | | 1 |
| What is interrupt latency? | | 2 |
| What is Noise Margin? Explain the procedure to determine
Noise Margin? | Cisco | 2 |
| Why don?t we use just one NMOS or PMOS transistor as a
transmission gate? | | 2 |
| For a 0.18um and 0.8um technology MOSFET, which has a higher
cutoff frequency? | | 1 |
| What is the most complicated/valuable program you written in
C/C++? | Intel | 6 |
| Explain about stuck at fault models, scan design, BIST and
IDDQ testing? | Intel | 1 |
| What is Fowler-Nordheim Tunneling? | Intel | 1 |
| What is a linked list? Explain the 2 fields in a linked list? | Intel | 1 |
| Are you familiar with the term snooping? | Intel | 1 |
| What products have you designed which have entered high
volume production? | Intel | 1 |
| What happens to delay if you increase load capacitance? | | 2 |
| Differences between blocking and Non-blocking statements in
Verilog? | Intel | 3 |
| What are set up time & hold time constraints? What do they
signify? | | 1 |
| What happens to delay if we include a resistance at the
output of a CMOS circuit? | | 1 |
| Who provides the DRC rules? | Intel | 3 |
| Explain Clock Skew? | Intel | 2 |
| Explain the concept of a Clock Divider Circuit? Write a VHDL
code for the same? | Intel | 1 |
| What types of high speed CMOS circuits have you designed? | Intel | 1 |
| Differences between D-Latch and D flip-flop? | Intel | 6 |
| |
| For more VLSI Interview Questions Click Here |
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