| Other VLSI Interview Questions |
| |
| Question | Asked @ | Answers |
| |
| Suppose you have a combinational circuit between two
registers driven by a clock. What will you do if the delay
of the combinational circuit is greater than your clock
signal? (You can't resize the combinational circuit
transistors)
| | 3 |
| Differences between DRAM and SRAM? | Intel | 4 |
| How do you detect if two 8-bit signals are same? | | 4 |
| What are the different limitations in increasing the power
supply to reduce delay? | | 1 |
| What is the difference between = and == in C? | Intel | 5 |
| Implement an Inverter using a single transistor? | Intel | 1 |
| What is setup time and hold time? | Intel | 1 |
| For a single computer processor computer system, what is the
purpose of a processor cache and describe its operation? | Intel | 1 |
| For a 0.18um and 0.8um technology MOSFET, which has a higher
cutoff frequency? | | 1 |
| Why don?t we use just one NMOS or PMOS transistor as a
transmission gate? | | 2 |
| Factors affecting Power Consumption on a chip? | Intel | 1 |
| Explain the difference between write through and write back
cache. | Intel | 1 |
| Differences between blocking and Non-blocking statements in
Verilog? | Intel | 3 |
| Explain about stuck at fault models, scan design, BIST and
IDDQ testing? | Intel | 1 |
| Have you studied pipelining? List the 5 stages of a 5 stage
pipeline. Assuming 1 clock per stage, what is the latency of
an instruction in a 5 stage machine? What is the throughput
of this machine ? | Intel | 2 |
| A circuit has 1 input X and 2 outputs A and B. If X = HIGH
for 4 clock ticks, A = 1. If X = LOW for 4 clock ticks, B =
1. Draw a state diagram for this Spec? | Intel | 1 |
| You have a driver that drives a long signal & connects to an
input device. At the input device there is either overshoot,
undershoot or signal threshold violations, what can be done
to correct this problem? | Intel | 3 |
| Have you studied pipelining? List the 5 stages of a 5 stage
pipeline. Assuming 1 clock per stage, what is the latency
of an instruction in a 5 stage machine? What is the
throughput of this machine ? | Intel | 2 |
| What happens to delay if we include a resistance at the
output of a CMOS circuit? | | 1 |
| For f = AB+CD if B is S-a-1, what r the test vectors needed
to detect the fault? | Intel | 1 |
| |
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