| Other VLSI Interview Questions |
| |
| Question | Asked @ | Answers |
| |
| For a single computer processor computer system, what is the
purpose of a processor cache and describe its operation? | Intel | 1 |
| Differences between DRAM and SRAM? | Intel | 4 |
| What is validation? | Intel | 1 |
| Who provides the DRC rules? | Intel | 3 |
| What is Cross Talk? | Intel | 2 |
| What happens to delay if you increase load capacitance? | | 2 |
| How many bit combinations are there in a byte? | Intel | 4 |
| What is SPICE? | Intel | 1 |
| what is Latch up?How to avoid Latch up? | | 2 |
| Suppose you have a combinational circuit between two
registers driven by a clock. What will you do if the delay
of the combinational circuit is greater than your clock
signal? (You can't resize the combinational circuit
transistors)
| | 3 |
| What is a linked list? Explain the 2 fields in a linked list? | Intel | 1 |
| How to find the read failiure probablity in SRAM?
| | 1 |
| Implement an Inverter using a single transistor? | Intel | 1 |
| Implement D flip-flop with a couple of latches? Write a VHDL
Code for a D flip-flop? | Intel | 3 |
| Are you familiar with VHDL and/or Verilog? | Intel | 4 |
| Why don?t we use just one NMOS or PMOS transistor as a
transmission gate? | | 2 |
| What are the different limitations in increasing the power
supply to reduce delay? | | 1 |
| Differences between blocking and Non-blocking statements in
Verilog? | Intel | 3 |
| Why is Extraction performed? | Intel | 1 |
| Explain about stuck at fault models, scan design, BIST and
IDDQ testing? | Intel | 1 |
| |
| For more VLSI Interview Questions Click Here |
Did you received any Funny E-Mails from your Friends and like to share with rest of our friends? Yeah!! you can post that stuff 
Site Map
