| Other VLSI Interview Questions |
| |
| Question | Asked @ | Answers |
| |
| Give the various techniques you know to minimize power
consumption? | | 3 |
| Implement D flip-flop with a couple of latches? Write a VHDL
Code for a D flip-flop? | Intel | 3 |
| Have you studied pipelining? List the 5 stages of a 5 stage
pipeline. Assuming 1 clock per stage, what is the latency
of an instruction in a 5 stage machine? What is the
throughput of this machine ? | Intel | 2 |
| For a 0.18um and 0.8um technology MOSFET, which has a higher
cutoff frequency? | | 1 |
| How to find the read failiure probablity in SRAM?
| | 1 |
| Suppose you have a combinational circuit between two
registers driven by a clock. What will you do if the delay
of the combinational circuit is greater than your clock
signal? (You can't resize the combinational circuit
transistors)
| | 3 |
| What are the different limitations in increasing the power
supply to reduce delay? | | 1 |
| What happens to delay if we include a resistance at the
output of a CMOS circuit? | | 1 |
| What is SPICE? | Intel | 1 |
| What happens to delay if you increase load capacitance? | | 2 |
| What is FPGA? | Intel | 2 |
| A circuit has 1 input X and 2 outputs A and B. If X = HIGH
for 4 clock ticks, A = 1. If X = LOW for 4 clock ticks, B =
1. Draw a state diagram for this Spec? | Intel | 1 |
| What is the most complicated/valuable program you written in
C/C++? | Intel | 6 |
| what is body effect? | | 1 |
| What is Fowler-Nordheim Tunneling? | Intel | 1 |
| Differences between DRAM and SRAM? | Intel | 4 |
| What is charge sharing? | Intel | 1 |
| Explain the concept of a Clock Divider Circuit? Write a VHDL
code for the same? | Intel | 1 |
| What are the limitations in increasing the power supply to
reduce delay? | | 1 |
| For f = AB+CD if B is S-a-1, what r the test vectors needed
to detect the fault? | Intel | 1 |
| |
| For more VLSI Interview Questions Click Here |
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