| Other VLSI Interview Questions |
| |
| Question | Asked @ | Answers |
| |
| For a 0.18um and 0.8um technology MOSFET, which has a higher
cutoff frequency? | | 1 |
| Explain about stuck at fault models, scan design, BIST and
IDDQ testing? | Intel | 1 |
| Implement an Inverter using a single transistor? | Intel | 1 |
| What types of high speed CMOS circuits have you designed? | Intel | 1 |
| Why is Extraction performed? | Intel | 1 |
| Factors affecting Power Consumption on a chip? | Intel | 1 |
| what is Latch up?How to avoid Latch up? | | 2 |
| Are you familiar with the term snooping? | Intel | 1 |
| What are set up time & hold time constraints? What do they
signify? | | 1 |
| Which gate is normally preferred while implementing circuits
using CMOS logic, NAND or NOR? Why? | Intel | 6 |
| what is body effect? | | 1 |
| What are the main issues associated with multiprocessor
caches and how might you solve them? | Intel | 1 |
| What is SPICE? | Intel | 1 |
| What is LVS, DRC? | Intel | 4 |
| What is Fowler-Nordheim Tunneling? | Intel | 1 |
| What is the difference between = and == in C? | Intel | 5 |
| How many bit combinations are there in a byte? | Intel | 4 |
| How do you detect a sequence of "1101" arriving serially
from a signal line?
| nvidia | 2 |
| Explain the difference between write through and write back
cache. | Intel | 1 |
| What are the different limitations in increasing the power
supply to reduce delay? | | 1 |
| |
| For more VLSI Interview Questions Click Here |
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