| Other VLSI Interview Questions |
| |
| Question | Asked @ | Answers |
| |
| what is short Channel effect. | | 1 |
| What is the difference between = and == in C? | Intel | 5 |
| A circuit has 1 input X and 2 outputs A and B. If X = HIGH
for 4 clock ticks, A = 1. If X = LOW for 4 clock ticks, B =
1. Draw a state diagram for this Spec? | Intel | 1 |
| Define threshold voltage? | Intel | 3 |
| How to find the read failiure probablity in SRAM?
| | 1 |
| Differences between blocking and Non-blocking statements in
Verilog? | Intel | 3 |
| Which gate is normally preferred while implementing circuits
using CMOS logic, NAND or NOR? Why? | Intel | 6 |
| For f = AB+CD if B is S-a-1, what r the test vectors needed
to detect the fault? | Intel | 1 |
| What is a linked list? Explain the 2 fields in a linked list? | Intel | 1 |
| Implement F = AB+C using CMOS gates? | Intel | 1 |
| What are the limitations in increasing the power supply to
reduce delay? | | 1 |
| Give the various techniques you know to minimize power
consumption? | | 3 |
| What products have you designed which have entered high
volume production? | Intel | 1 |
| Why is Extraction performed? | Intel | 1 |
| What is charge sharing? | Intel | 1 |
| what is Latch up?How to avoid Latch up? | | 2 |
| How do you detect if two 8-bit signals are same? | | 4 |
| Are you familiar with VHDL and/or Verilog? | Intel | 4 |
| What is LVS, DRC? | Intel | 4 |
| What are the main issues associated with multiprocessor
caches and how might you solve them? | Intel | 1 |
| |
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