| Other VLSI Interview Questions |
| |
| Question | Asked @ | Answers |
| |
| Explain about stuck at fault models, scan design, BIST and
IDDQ testing? | Intel | 1 |
| Are you familiar with the term snooping? | Intel | 1 |
| What types of high speed CMOS circuits have you designed? | Intel | 1 |
| How do you detect a sequence of "1101" arriving serially
from a signal line?
| nvidia | 2 |
| What is interrupt latency? | | 2 |
| Why don?t we use just one NMOS or PMOS transistor as a
transmission gate? | | 2 |
| What happens to delay if we include a resistance at the
output of a CMOS circuit? | | 1 |
| Differences between Signals and Variables in VHDL? If the
same code is written using Signals and Variables what does
it synthesize to? | Intel | 1 |
| Have you studied pipelining? List the 5 stages of a 5 stage
pipeline. Assuming 1 clock per stage, what is the latency of
an instruction in a 5 stage machine? What is the throughput
of this machine ? | Intel | 2 |
| What is Noise Margin? Explain the procedure to determine
Noise Margin? | Cisco | 2 |
| what is Latch up?How to avoid Latch up? | | 2 |
| Implement an Inverter using a single transistor? | Intel | 1 |
| Which gate is normally preferred while implementing circuits
using CMOS logic, NAND or NOR? Why? | Intel | 6 |
| What is Fowler-Nordheim Tunneling? | Intel | 1 |
| What is the most complicated/valuable program you written in
C/C++? | Intel | 6 |
| Differences between DRAM and SRAM? | Intel | 4 |
| What is SPICE? | Intel | 1 |
| Implement D flip-flop with a couple of latches? Write a VHDL
Code for a D flip-flop? | Intel | 3 |
| Factors affecting Power Consumption on a chip? | Intel | 1 |
| Give the expression for CMOS switching power dissipation? | | 2 |
| |
| For more VLSI Interview Questions Click Here |
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