| Other VLSI Interview Questions |
|| Asked @
|Explain the various Capacitances associated with a
transistor and which one of them is the most prominent?
|what is conductance and valence band?
|| ||1 |
|Have you studied pipelining? List the 5 stages of a 5 stage
pipeline. Assuming 1 clock per stage, what is the latency
of an instruction in a 5 stage machine? What is the
throughput of this machine ?
|What types of high speed CMOS circuits have you designed?
|Why do we use a Clock tree?
|If the current thru the poly is 20nA and the contact can
take a max current of 10nA how would u overcome the problem?
|WHAT IS THE DIFFERENCE BETWEEN TESTING AND VERIFICATION OF
|What is Fermi level?
|| ||5 |
|How to find the read failiure probablity in SRAM?
|| ||2 |
|Are you familiar with VHDL and/or Verilog?
|Why is OOPS called OOPS? (C++)
|For a 0.18um and 0.8um technology MOSFET, which has a higher
|| ||2 |
|For more VLSI Interview Questions Click Here |