library ieee;
use ieee.std_logic_1164.all;

entity d_ff is
port(d,clk:in std_logic;
     q,q'bar:out std_logic);
end d_ff;

architecture a_d_ff of d_ff is
begin
process(clk)
begin
if rising_edge(clk) then
q<=d;
q'bar<=not d;
end if;
end process;
end a_d_ff;

ibrary IEEE;
use IEEE.STD_LOGIC_1164.all;

entity gh_DFF is
	 port(
		 D    : in STD_LOGIC;
		 CLK  : in STD_LOGIC;
		 rst  : in STD_LOGIC;
		 Q    : out STD_LOGIC
	     );
end gh_DFF;

architecture a of gh_DFF is
begin

process(CLK,rst)
begin
	if (rst = '1') then
		Q <= '0';
	elsif (rising_edge(CLK)) then
		Q <= D;
	end if;
end process;

end a;

D flip-flop can be implemented by using 2 D-Latches.



   ----------       -----------
--|Din     Q |-----|Din       Q|---output of Flop
  |  D-latch1|     | D-latch2  |
  |    ^     |     |    ^      |
   ----|-----       ----|------
Clk -------------not-----