ALLInterview.com :: Home Page            
 Advertise your Business Here     
Browse  |   Placement Papers  |   Company  |   Code Snippets  |   Certifications  |   Visa Questions
Post Question  |   Post Answer  |   My Panel  |   Search  |   Articles  |   Topics  |   ERRORS new
   Refer this Site  Refer This Site to Your Friends  Site Map  Bookmark this Site  Set it as your HomePage  Contact Us     Login  |  Sign Up                      
Google
   
 
Categories >> Engineering >> Electronics Communications
 
 


 

 
 Civil Engineering interview questions  Civil Engineering Interview Questions (3011)
 Mechanical Engineering interview questions  Mechanical Engineering Interview Questions (3270)
 Electrical Engineering interview questions  Electrical Engineering Interview Questions (13224)
 Electronics Communications interview questions  Electronics Communications Interview Questions (2348)
 Chemical Engineering interview questions  Chemical Engineering Interview Questions (407)
 Aeronautical Engineering interview questions  Aeronautical Engineering Interview Questions (76)
 Bio Engineering interview questions  Bio Engineering Interview Questions (16)
 Metallurgy interview questions  Metallurgy Interview Questions (79)
 Industrial Engineering interview questions  Industrial Engineering Interview Questions (162)
 Instrumentation interview questions  Instrumentation Interview Questions (2317)
 Automobile Engineering interview questions  Automobile Engineering Interview Questions (104)
 Mechatronics Engineering interview questions  Mechatronics Engineering Interview Questions (38)
 Marine Engineering interview questions  Marine Engineering Interview Questions (43)
 Power Plant Engineering interview questions  Power Plant Engineering Interview Questions (73)
 Engineering AllOther interview questions  Engineering AllOther Interview Questions (1189)
Question
1,what is the different between signal and variables in 
VHDL?
2,what is the different between function and procedure in 
VHDL?
 Question Submitted By :: Venkat Stony
I also faced this Question!!     Rank Answer Posted By  
 
  Re: 1,what is the different between signal and variables in VHDL? 2,what is the different between function and procedure in VHDL?
Answer
# 1
Hello,
A function returns 1 value whereas a procedure can return
multiple values? Could someone elucidate this for me? Also, I
am confused about the scope of signals. If I declare a signal
within an architecture, does the scope of this signal extend
to functions declared within processes in the architecture? If
not, is there a way to do this without passing the signals? I
would like to call functions in a way resembling scripts that
allowed for greater code readability.
 
Is This Answer Correct ?    0 Yes 3 No
Jimmy.gugon
 

 
 
 
Other Electronics Communications Interview Questions
 
  Question Asked @ Answers
 
can any one say what are the non-scientific calculators?..i use casio ms350...wtr it is a scientific or non-scientific.... Microtek 1
what is the different between opamp,comparator and amplifier?   2
why the microcontroller so called 8051?/ and why the IC starts with 74? Bhel 6
what is rectifier? ISRO 11
what is body effect? BHEL 1
how can i prepare for campus placement? Wipro 2
Sparking occur when a load is switched off because the circuit has high a.) Inductance b.) Capacitance c.) Resistance d.) None BSNL 9
why number of scanning lines per frame always odd in television?   1
which language is not object oriented? BSNL 3
what is the physical need to find 3bd frequencies?   3
what is ip NSN 6
what is ALE?what is it's function?   4
 
For more Electronics Communications Interview Questions Click Here 
 
 
 
 
 


   
Copyright Policy  |  Terms of Service  |  Articles  |  Site Map  |  RSS Site Map  |  Contact Us
   
Copyright 2013  ALLInterview.com.  All Rights Reserved.

ALLInterview.com   ::  KalAajKal.com