| Other VLSI Interview Questions |
| |
| Question | Asked @ | Answers |
| |
| Suppose you have a combinational circuit between two
registers driven by a clock. What will you do if the delay
of the combinational circuit is greater than your clock
signal? (You can't resize the combinational circuit
transistors)
| | 3 |
| What are the main issues associated with multiprocessor
caches and how might you solve them? | Intel | 1 |
| What is charge sharing? | Intel | 1 |
| Define threshold voltage? | Intel | 3 |
| What happens when the gate oxide is very thin? | Intel | 2 |
| You have a driver that drives a long signal & connects to an
input device. At the input device there is either overshoot,
undershoot or signal threshold violations, what can be done
to correct this problem? | Intel | 3 |
| Explain about stuck at fault models, scan design, BIST and
IDDQ testing? | Intel | 1 |
| What types of high speed CMOS circuits have you designed? | Intel | 1 |
| How many bit combinations are there in a byte? | Intel | 4 |
| What is FPGA? | Intel | 2 |
| what is Latch up?How to avoid Latch up? | | 2 |
| Explain the difference between write through and write back
cache. | Intel | 1 |
| Which gate is normally preferred while implementing circuits
using CMOS logic, NAND or NOR? Why? | Intel | 6 |
| For a 0.18um and 0.8um technology MOSFET, which has a higher
cutoff frequency? | | 1 |
| A circuit has 1 input X and 2 outputs A and B. If X = HIGH
for 4 clock ticks, A = 1. If X = LOW for 4 clock ticks, B =
1. Draw a state diagram for this Spec? | Intel | 1 |
| What is Fowler-Nordheim Tunneling? | Intel | 1 |
| For f = AB+CD if B is S-a-1, what r the test vectors needed
to detect the fault? | Intel | 1 |
| Give the various techniques you know to minimize power
consumption? | | 3 |
| Explain Clock Skew? | Intel | 2 |
| What is LVS, DRC? | Intel | 4 |
| |
| For more VLSI Interview Questions Click Here |
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