| Other VLSI Interview Questions |
| |
| Question | Asked @ | Answers |
| |
| Give the various techniques you know to minimize power
consumption? | | 3 |
| Have you studied pipelining? List the 5 stages of a 5 stage
pipeline. Assuming 1 clock per stage, what is the latency of
an instruction in a 5 stage machine? What is the throughput
of this machine ? | Intel | 2 |
| A circuit has 1 input X and 2 outputs A and B. If X = HIGH
for 4 clock ticks, A = 1. If X = LOW for 4 clock ticks, B =
1. Draw a state diagram for this Spec? | Intel | 1 |
| Are you familiar with the term snooping? | Intel | 1 |
| How to find the read failiure probablity in SRAM?
| | 1 |
| For a single computer processor computer system, what is the
purpose of a processor cache and describe its operation? | Intel | 1 |
| Give the expression for CMOS switching power dissipation? | | 2 |
| Differences between blocking and Non-blocking statements in
Verilog? | Intel | 2 |
| What is a linked list? Explain the 2 fields in a linked list? | Intel | 1 |
| What is LVS, DRC? | Intel | 4 |
| What is Fowler-Nordheim Tunneling? | Intel | 1 |
| What is setup time and hold time? | Intel | 1 |
| Implement F = AB+C using CMOS gates? | Intel | 1 |
| Implement an Inverter using a single transistor? | Intel | 1 |
| Explain the concept of a Clock Divider Circuit? Write a VHDL
code for the same? | Intel | 1 |
| How do you detect a sequence of "1101" arriving serially
from a signal line?
| nvidia | 2 |
| What happens to delay if we include a resistance at the
output of a CMOS circuit? | | 1 |
| What are the limitations in increasing the power supply to
reduce delay? | | 1 |
| Why don?t we use just one NMOS or PMOS transistor as a
transmission gate? | | 2 |
| What are the different limitations in increasing the power
supply to reduce delay? | | 1 |
| |
| For more VLSI Interview Questions Click Here |
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