threshold voltage is defined as the minimum voltage that 
required to make the transistor ON. transistor may be 
either NMOS or PMOS.For NMOS the value of threshold voltage 
is positive value and for PMOS the value of threshold 
voltage is negative value.

thresold voltage is minimum voltage that requires to turn 
on the mosfet transister & that conducts the drain current

threshold voltage can be defined as the the voltage requied 
to create a strong inversion.

Polymorphism is the ability of a message to be written in
more than one form

Signals updates a value after some "delta" time or at the
end of the process. But variable updates a value immediately.

Both variable and signals are synthesizable. 
Designer should know hoe to use these 2 objects.

Ex: Signal usage
Library IEEE;
use IEEE.std_logic_1164.all;
entity xor_sig is
port (
A, B, C: in STD_LOGIC;
X, Y: out STD_LOGIC
);
end xor_sig;
architecture SIG_ARCH of xor_sig is
signal D: STD_LOGIC;
begin
SIG:process (A,B,C)
begin
D <= A; -- ignored !!
X <= C xor D;
D <= B; -- overrides !!
Y <= C xor D;
end process;
end SIG_ARCH;

Variable usage:
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity xor_var is
port (
A, B, C: in STD_LOGIC;
X, Y: out STD_LOGIC
);
end xor_var;
architecture VAR_ARCH of xor_var is
begin
VAR:process (A,B,C)
variable D: STD_LOGIC;
begin
D := A;
X <= C xor D;
D := B;
Y <= C xor D;
end process;
end VAR_ARCH;

Blocking statements are executed on after another 
represented by '='

Ex. lets take two variables
reg A:0;
reg B:1;
initial
begin
A = B;
B = A;
end

Ans  
A = 1
B = 1

Non Blocking
instructions are executed concurrently 
represented by '=>'

Ex. lets take two variables
reg A:0;
reg B:1;
initial
begin
A = B;
B = A;
end

Ans  
A = 1
B = 0

cp mistake in 1st one.
-----------------------------------

Blocking statements are executed on after another 
represented by '='

Ex. lets take two variables
reg A:0;
reg B:1;
initial
begin
A = B;
B = A;
end

Ans  
A = 1
B = 1

Non Blocking
instructions are executed concurrently 
represented by '<='

Ex. lets take two variables
reg A:0;
reg B:1;
initial
begin
A <= B;
B <= A;
end

Ans  
A = 1
B = 0

Yes,the explanation is ok but after a particular time
units,the value of B must be equal to 1 no?

cmos design combination of both pmos and nmos.pmos is pull
up network.nmos pull down network.A TRANISTOR IS CONNECTED
SERIES     WITH B TRANSISTOR.THE SERIES COMBINATION OF BOTH
A AND B TRANSISTOR CONNECTED PARALLEL WITH C TRANSISTOR(IN
PULL DOWN CKT).THEN APPLY DUALITY PROPERTY TO PMOS.THEN
FINAL OUTPUT IS COMPLEMENTED BY CMOS INVERTER.THIS FUNCTION
IMPLEMENTED IN DIFFERENT LOGICS
1.CMOS LOGIC
2.C2 MOS LOGIC
3.NP LOGIC
4.DYNAMIC LOGIC
5.PASS TRANSISTOR LOGIC
6.DOMINO LOGIC
7.DIFFERENTIAL CASCADE VOLTAGE SWITCH LOGIC
8.PSUEDO NMOS LOGIC

fpga are programmable digital logic chips,what that means 
is that you can program them to do almost any digital 
function

FPGA is Field Programmable Gate array. We can implement any
digital logic functions in FPGA.

field programmable gate array,it is the tool which is 
readily available in market to simulate the language

Simulation Program with Integrated Circuit Emphasis.
A program widely used to simulate the performance of analog
electronic systems and mixed mode analog and digital
systems. SPICE solves sets of non-linear differential
equations in the frequency domain, steady state and time
domain and can simulate the behavior of transistor and gate
designs. Developed at the University of California at
Berkeley in the mid-1970s, there are enhanced versions of
SPICE provided by several software companies. PSpice is a
version for personal computers such as DOS, Windows and Mac.

IDDQ testing is used for testing the library cells. Meaning
if any faults are there in our design we are going for DFT.
If any faults are there in the library itself we are doing
IDDQ testing.

SETUP time : Minimum time the data should be stable before
the arrival of clock edge

HOLD time : Minum time data shuold be stable after the
arrival of clock edge.