There are 8bit combinations in a byte.

I have worked on design consit of 5 stage pipeline 
processor.

With 5 stage pipeline it takes minimum 5 clock cycle to to 
execute a instuction. So latency of instuction is5 clock 
cycles.

Through put is one instruction per clock cycle + initial 
overhed of 4 clock cycle

1.Instruction fetch
2.decode instruction and read register files
3.execute
4.data to access from memory
5.write back

throughput is the total amount of work done in a given time,

Yes. 
1.Memory processor bus= high speed, short length.
2.I/O bus.
3.Backplane bus= General purpose bus ex PCI

NAND gate is normally prefered because the mobility of 
holes in NAND gate is three times greater than mobility of 
electron.

if u look at the structure of cmos-nand gate,u cud find the
parallel pmos pull-up transistor configuration whereas in
cmos-nor gate its series config,so the effective resistance
offered by 2-pmos transistors even when they r conducting
due to small Rds (drain-to-source resistance)are smaller in
comparison to the same offered by series pmos in nor
gate..hence the current delivered to the output during HIGH
o/p condition is more for nand gate,due to which it has the
ability to drive more no. of loads of similar type ,thus
offer improved FAN-OUT than cmos-nor gate. 
I feel tat this could be the reason..it is true fact as per
WAKERLY text book..but there cud be 'n' no of other reasons
too..think over 

thankx..
balaji kalluri

NAAND gate is more preferred than NOR because high to low
and low to high transition time is less in NAND as compared
to NOR

As because the logical effort of Nand gate is lower than
that of the Nor gate the time taken to drive same capacitor
with same input slew is lesser for Nand that that of Nor.
Means Nand is faster than Nor.

nand gate is preferred because it has high driving 
capacity.

NAND is a better gate for design than NOR because at the 
transistor level the mobility of electrons of NAND is 
normally three times that of holes compared to NOR and thus 
the NAND is a faster gate. The gate-leakage in NAND 
structures is much lower. If you consider t_phl and t_plh 
delays you will find that it is more symmetric in case of 
NAND (the delay profile), but for NOR, one delay is much 
higher than the other(obviously t_plh is higher since the 
higher resistance PMOSs are in series connection which 
again increases the resistance).

IN SPARTAN 3E BOARD.. THE INTERNAL CLOCK FREQUENCY IS 
16MHZ... IF WE WANT TO INTERFACING THE EXT DIPLAY DEVICES
WE WON'T RUN IT WITH A NORMAL CLOCK FREQ(16 
MHZ)....THATSWHY I HAVE TO CREATED NEW CLOCK PULSE WITH THE 
FREQ OF 1HZ BY DEVIDING THE CLOCK..... TAKE THE NORMAL CLK 
AS A REFERENCE...THIS IS KNOWN AS CLOCK DIVIDER CONCEPT...

ENTITY CLK_DIV IS
    PORT(CLK: IN STD_LOGIC;
          NEWCLK:OUT STD_LOGIC);
END CLK_DIV
ARCH BEH OF CLK_DIV IS
VARIABLE COUNT:INTEGER:=0;
SIGNAL CLKN:STD_LOGIC; 
BEGIN
PROCESS(CLK)
BEGIN
IF CLK='1' AND CLK'EVENT THEN
COUNT:=COUNT+1;
IF COUNT=8000000 THEN
    NEWCLK<= NOT CLKN 
    COUNT:=0;
END PROCESS;
END BEH;

This is a phenomena associated with the gate thickness of a 
transistor. When the thickness of oxide is very small there 
exists a possibilty that electrons pass directly between 
source and gate. This is a seond order effect and limits 
the scaling down of transistor size.

give input at base and connect resistor at collector and 
gnd at emitter,vcc at collector finaaly take output at 
collector.

In series of Inverter is placed, the charge sharing happen 
between the input capacitance with the help of an load 
capacitane but we cant get the desired logical output. 

Remedies:

The load capacitane must be ten times greater than input 
capacitance.

Crosstalk is coupling effect of capacitance that takes place
between a weak net and an aggressor net