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If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?
Intel
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48
Insights of a Tri-state inverter?
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39
What is Fowler-Nordheim Tunneling?
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354
Implement an Inverter using a single transistor?
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312
What is clock feed through?
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57
What r the phenomenon which come into play when the devices are scaled to the sub-micron lengths?
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43
Different ways of implementing a comparator?
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59
What is Cross Talk?
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What is validation?
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275
Who provides the DRC rules?
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812
What is LVS, DRC?
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Why is Extraction performed?
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Explain Custom Design Flow?
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Explain ASIC Design Flow?
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Explain the Various steps in Synthesis?
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what is conductance and valence band?
60
Cross section of an NMOS transistor?
57
Intel
What is the build-in potential?
76
What are the main issues associated with multiprocessor caches and how might you solve them?
44
Intel
Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
52
Intel
Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly, M1 and diffusion layers etc?
37
Intel
Explain the working of 4-bit Up/down Counter?
66
Intel
Tell me the parameters as many as possible you know that used to character an amplifier?
66
How to improve these parameters? (Cascode topology, use long channel transistors)
64
What does the above code synthesize to?
54
Intel
How can you construct both PMOS and NMOS on a single substrate?
61
Intel
Are you familiar with VHDL and/or Verilog?
75
Intel
Draw the Layout of an Inverter?
82
Intel
What is Noise Margin? Explain the procedure to determine Noise Margin?
68
What is a D-latch? Write the VHDL Code for it?
64
Intel
Have you studied buses? What types?
32
Intel
Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.
82
Intel
What happens if we use an Inverter instead of the Differential Sense Amplifier?
77
Different ways of implementing a comparator?
59
Intel
Explain Custom Design Flow?
58
Intel
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