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  Question  Asked @ Answers Views     select
 
in a sn SR latch made by using cross coupling of two nand gates, if both S andR inputs set o then it will result ISRO  1  233
look at following code void foo(void) { unsigned int a = 6; int b = -20; int c = (a+b > 6) ? 1:0; } o/p is 1 why explain promotion rules  1  376
verify nmos passes good logic 0 and passes bad logic 1.also verify that pmos passes good logic 1 and passes bad logic 0. HP   2  2105
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.  0  745
What is the mealy and moore machine's state diagram that can detect 3 consecutive heads of 3 coins ?  2  1570
What is an anti aliasing filter? Why is it required? Honeywell   6  4297
How do you implement a fourth order Butterworth LP filter at 1kHz if sampling frequency is 8 kHz? Honeywell  1  2544
please send me the faq's in technical interviews on cand datastructures , unix(shell scripting).  0  654
can please tel me faq's asking in interviews on microcontrollers TCS  0  933
what is the difference between the testing and verification? INTEL  0  1096
im using I2C communication, in that first im sending address of thesalve and then data then after i want to read the data which i was sent recently, in that case before im reading is there any need to send a stop bit before read.  1  1519
PROVIDE ME NOTES ON EMBEDDED TCHNLOGY TCS  0  808
Write a code in C / Verilog to implement a basic FIR filter. Need an answer.  1  3712
I have code and test bench however it is not working porperly. Need help to get it working. module fsm(clock,reset,coin,vend,state,change); \\these are the inputs and the outputs. input clock; input reset; input [2:0]coin; output vend; output [2:0]state; output [2:0]change; \\i need to define the registers as change,coin and vend reg vend; reg [2:0]change; wire [2:0]coin; \\my coins are declared as parameters to make reading better. parameter [2:0]NICKEL=3b001; parameter [2:0]DIME=3b010; parameter [2:0]NICKEL_DIME=3b011; parameter [2:0]DIME_DIME=3b100; parameter [2:0]QUARTER=3b101; \\MY STATES ARE ALSO PARAMETERS . I DONT WANT TO MAKE YOU READ \\IN MACHINE LANGUAGE parameter [2:0]IDLE=3b000; parameter [2:0]FIVE=3b001; parameter [2:0]TEN=3b010; parameter [2:0]FIFTEEN=3b011; parameter [2:0]TWENTY=3b100; parameter [2:0]TWENTYFIVE=3b101; \\AS ALWAYS THE STATES ARE DEFINED AS REG reg [2:0]state,next_state; \\MY MACHINE WORKS ON STATE AND COIN always @(state or coin) begin next_state=0; \\VERYFIRST NEXT STATE IS GIVEN ZERO case(state) IDLE: case(coin) \\THIS IS THE IDLE STATE NICKEL: next_state=FIVE; DIME: next_state=TEN; QUARTER: next_state=TWENTYFIVE; default: next_state=IDLE; endcase FIVE: case(coin) \\THIS IS THE SECOND STATE NICKEL: next_state=TEN; DIME: next_state=FIFTEEN; QUARTER: next_state=TWENTYFIVE; //change=NICKEL default: next_state=FIVE; endcase TEN: case(coin) \\THIS IS THE THIRD STATE NICKEL: next_state=FIFTEEN; DIME: next_state=TWENTY; QUARTER: next_state=TWENTYFIVE; //change=DIME default: next_state=TEN; endcase FIFTEEN: case(coin) \\THIS IS THE FOURTH STATE NICKEL: next_state=TWENTY; DIME: next_state=TWENTYFIVE; QUARTER: next_state=TWENTYFIVE; //change==NICKEL_DIME default: next_state=FIFTEEN; endcase TWENTY: case(coin) \\THIS IS THE FIFTH STATE NICKEL: next_state=TWENTYFIVE; DIME: next_state=TWENTYFIVE; //change=NICKEL QUARTER: next_state=TWENTYFIVE; //change==DIME_DIME default: next_state=TWENTY; endcase TWENTYFIVE: next_state=IDLE; \\THE NEXT STATE HERE IS THE RESET default : next_state=IDLE; endcase end always @(clock) begin \\WHENEVER I GIVE A RESET I HAVE TO MAKE THE STATE TO IDLE AND VEND TO 1 if(reset) begin state <= IDLE; vend <= 1b0; // change <= 3b000; end \\THE CHANGE ALSO HAS TO BECOME NONE else state <= next_state; case (state) \\HERE WE DECIDE THE NEXT STATE \\ALL THE STATES ARE DEFINED HERE AND THE OUTPUT IS ALSO GIVEN IDLE: begin vend <= 1b0; change <=3d0; end FIVE: begin vend <= 1b0; if (coin==QUARTER) change <=NICKEL; else change <=3d0; TEN: begin vend <= 1b0; if (coin==QUARTER) change <=DIME; else change <= 3d0; FIFTEEN : begin vend <= 1b0; if (coin==QUARTER) change <=NICKEL_DIME; else change TWENTY : begin vend <= 1b0; if (coin==DIME) change <=NICKEL; else if (coin==QUARTER) TWENTYFIVE : begin vend <= 1b1; change <=3d0; end default: state <= IDLE; endcase end endmodule module test; \\THE INPUT IN THE FSM MODULE ARE REG HERE reg clock,reset; reg [2:0]coin; \\THE OUTPUT IN THE FSM MODULE ARE WIRES HERE wire vend; wire [2:0]state; wire [2:0]change; \\THE PARAMETERS AGAIN FOR THE COIN AND STATE parameter [2:0]IDLE=3b000; parameter [2:0]FIVE=3b001; parameter [2:0]TEN=3b010; parameter [2:0]FIFTEEN=3b011; parameter [2:0]TWENTY=3b100; parameter [2:0]TWENTYFIVE=3b101; parameter [2:0]NICKEL=3b001; parameter [2:0]DIME=3b010; parameter [2:0]NICKEL_DIME=3b011; parameter [2:0]DIME_DIME=3b100; parameter [2:0]QUARTER=3b101; \\I MONITOR THE TIME,DRINK,RESET,CLOCK,STATE AND CHANGE FOR CHANGES. initial begin $display("Time\tcoin\tdrink\treset\tclock\tstate\tchange"); $monitor("%g\t%b\t%b\t%b\t%b\t%d\t% d",$time,coin,vend,reset,clock,state,change); \\NEW FEATURE: MY MACHINE HAS THE FACILITY TO DUMP VARIABLES SO THAT \\ I CAN VIEW THEM USING A VCD VIEWER. $dumpvars; $dumpfile("file.vcd"); // Dump output file. \\THIS IS WHERE THE COINS ARE ADDED. clock=0; reset=1; \\FIRST LETS RESET THE MACHINE #2 reset=0; coin=NICKEL; \\CHECK FOR STATE 1 #2 reset=1; coin=2b00; #2 reset=0; coin=DIME; \\RESET AGAIN AND CHECK FOR STATE 2 #2 reset=1; coin=2b00; #2 reset=0; \\RESET AGAIN AND CHECK FOR STATE 5 coin=QUARTER; #2 reset=1; coin=2b00; #2 reset=0; \\RESET AGAIN AND CHECK FOR STATE 5 coin=NICKEL; #2 coin=NICKEL; #2 coin=NICKEL; #2 coin=NICKEL; #2 coin=NICKEL; #2 reset=1; coin=2b00; #2 reset=0; \\RESET AGAIN AND CHECK FOR STATE 5 AND SO ON coin=NICKEL; #2 coin=DIME; #2 coin=DIME; #2 reset=1; coin=2b00; #2 reset=0; coin=NICKEL; #2 coin=DIME; #2 coin=QUARTER; #2 reset=1; coin=2b00; #2 reset=0; coin=NICKEL; #2 coin=NICKEL; #2 coin=NICKEL; #2 coin=DIME; #2 reset=1; coin=2b00; #2 reset=0; coin=NICKEL; #2 coin=NICKEL; #2 coin=NICKEL; #2 coin=NICKEL; #2 coin=DIME; #2 reset=1; coin=2b00; #2 reset=0; coin=NICKEL; #2 coin=NICKEL; #2 coin=QUARTER; #2 reset=1; coin=2b00; #2 reset=0; coin=NICKEL; #2 coin=QUARTER; #2 reset=1; coin=2b00; #2 $finish; end \\THE CLOCK NEEDS TO TICK EVERY 2 TIME UNIT always #1 clock=~clock; //always @(state) // coin=!coin; initial begin if (reset) coin=2b00; end \\THIS IS WHERE I INSTANTIATE THE MACHINE fsm inst1(clock,reset,coin,vend,state,change); endmodule Intel  0  917
This program is in verilog and need help to get it working correctly. This is the code i have so far. Please help. Simple testbench would be great. Thanks\ 'define vend_a_drink {D,dispense,collect} = {IDLE,2'b11}; module drink_machine(nickel_in, dime_in, quarter_in, collect, nickel_out, dime_out, dispense, reset, clk) ; parameter IDLE=0,FIVE=1,TEN=2,TWENTY_FIVE=3, FIFTEEN=4,THIRTY=5,TWENTY=6,OWE_DIME=7; input nickel_in, dime_in, quarter_in, reset, clk; output collect, nickel_out, dime_out, dispense; reg collect, nickel_out, dime_out, dispense; reg [2:0] D, Q; /* state */ // synopsys state_vector Q always @ ( nickel_in or dime_in or quarter_in or reset ) begin nickel_out = 0; dime_out = 0; dispense = 0; collect = 0; if ( reset ) D = IDLE; else begin D = Q; case ( Q ) IDLE: if (nickel_in) D = FIVE; else if (dime_in) D = TEN; else if (quarter_in) D = TWENTY_FIVE; FIVE: if(nickel_in) D = TEN; else if (dime_in) D = FIFTEEN; else if (quarter_in) D = THIRTY; TEN: if (nickel_in) D = FIFTEEN; else if (dime_in) D = TWENTY; else if (quarter_in) 'vend_a_drink; TWENTY_FIVE: if( nickel_in) D = THIRTY; else if (dime_in) 'vend_a_drink; else if (quarter_in) begin 'vend_a_drink; nickel_out = 1; dime_out = 1; end FIFTEEN: if (nickel_in) D = TWENTY; else if (dime_in) D = TWENTY_FIVE; else if (quarter_in) begin 'vend_a_drink; nickel_out = 1; end THIRTY: if (nickel_in) 'vend_a_drink; else if (dime_in) begin 'vend_a_drink; nickel_out = 1; end else if (quarter_in) begin 'vend_a_drink; dime_out = 1; D = OWE_DIME; end TWENTY: if (nickel_in) D = TWENTY_FIVE; else if (dime_in) D = THIRTY; else if (quarter_in) begin 'vend_a_drink; dime_out = 1; end OWE_DIME: begin dime_out = 1; D = IDLE; end endcase end end always @ (posedge clk ) begin Q = D; end endmodule Intel  0  838
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In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why? 924  
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Explain sizing of the inverter? 954  
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The answer to the above question is breaking the combinational circuit and pipelining it. What will be affected if you do this? 461  
Explain CMOS Inverter transfer characteristics? 1312  
Implement a 2 I/P and gate using Tran gates? 984 Intel
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