what happen ehen synchronisation is done at below rated speed
I am getting above 60 V as open delta voltage against single
phase unit ICT at tertiary delta formed and ICT getting
trippped on NDR. ICT tested and found in order. PTs provided
on tertiary are tested and in order. what may be the reason?
what are factors to be consider to design a HT & LT motor?
What was your role in the silicon evaluation/product ramp?
What tools did you use?
hai now i am working as a electrical design engineer
in construction field can i get a job in oil and gass field
or power plant project as a electrical design engineer?
what is the power rating of CPU, CRT type moniter, LCD type